1. Field of the Invention
The present invention relates to a simplified process of fabricating thin film transistor (TFT).
2. Description of Related Art
In recent years, with the improvement of the semiconductor fabrication technology, the fabrication process of the thin film transistor (TFT) is being continuously simplified and the fabrication throughput is being increased. TFT is widely used in many fields, such as computer chip, mobile-phone chip and/or thin film transistor liquid crystal displayer (TFT LCD), etc. Taking TFT LCD as an example, the TFT is mainly used to control the loading of data for LCD, which primarily comprises the elements of a gate, a channel layer and source/drain, etc. However, the definitions of the gate, channel layer, source/drain, contact hole, and pixel electrode are commonly accomplished with five masks in the conventional fabrication process of TFT.
FIG. 1A to FIG. 1E are the sectional drawings for a prior method of fabricating TFT. Referring to FIG. 1A, first, a conductive layer (not given in the figure) is formed on the substrate 100; secondly, a photolithography process is performed to pattern the conductive layer for forming a gate 120 by a first mask (not shown).
Next, referring to FIG. 1B, a silicon nitride layer 130 is formed on the substrate 100 to cover the gate 120. Thereafter, an amorphous silicon layer 140 and an n+-type doped amorphous silicon layer 150 are sequentially formed on the silicon nitride layer 130.
Subsequently, referring to FIG. 1C, a photolithography process is performed to pattern the amorphous silicon layer 140 in FIGS. 1B and n+-type doped amorphous silicon layer 150 in FIG. 1B for forming a channel layer 160 and an ohmic contact layer 170 by a second mask (not shown). A metal layer 180 is then formed on the substrate 100.
Next, referring to FIG. 1D, a photolithography process is performed to pattern the metal layer 180 in FIG. 1C for forming a source/drain 190 by a third mask (not shown).
Next, referring to FIG. 1E, a dry etching process 195 is performed on the ohmic contact layer 170 by using the source/drain 190 as a mask, whereby removing the ohmic contact layer 170 on the gate 120 and exposing the channel layer 160.
Because the removing function is obtained by plasma etching via physical bombardment and chemical reaction during the dry etching process 195 as shown in FIG. 1E, the surface of the channel layer 160 will be damaged while the ohmic contact layer 170 is removed, which will lead to producing many dangling bonds so as to effect the electrical performance of the device. An annealing process has to be used again in order to repair the damaged surface.